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[AMD] Add ROCm 10 (gfx942 / gfx950) release images - #36434

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HaiShaw merged 11 commits into
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codex/rocm10-rc4-gfx942-950
Aug 28, 2026
Merged

HaiShaw merged 11 commits into
mainfrom
codex/rocm10-rc4-gfx942-950

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@bingxche

@bingxche bingxche commented Aug 26, 2026 •

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Summary

Add ROCm 10 release images for gfx942 (MI300/MI325) and gfx950 (MI350/MI355X) using AMD's stable wheel-based ROCm SDK.

Pinned stack:

  • Ubuntu 24.04 / Python 3.12
  • ROCm SDK 10.0.0
  • PyTorch 2.11.0 / torchvision 0.26.0 / torchaudio 2.11.0
  • Triton 3.8.0+git4cff872c
  • AITER c16d44b93a528b2a4bfd6d8d3409116d465872a9

Changes

  • Add gfx942-rocm1000 and gfx950-rocm1000 Docker targets. Each image installs only its target architecture's ROCm SDK and PyTorch device wheels.
  • Add a daily/manual ROCm 10 release workflow following the existing ROCm 7.2 flow. It publishes dated rocm10-mi30x and rocm10-mi35x tags to rocm/sgl-dev, then mirrors the same tags to lmsysorg/sglang-rocm.
  • Add explicit rocm10 support to the AMD PR, extra, and nightly workflows. The scheduled all matrix remains unchanged and continues to cover ROCm 7.2.4 and 7.2.0.
  • Extend the AMD dependency installer for the internal rocm1000 flavor, including its torch, MORI, and AITER compatibility handling.
  • Remove hardcoded ROCm version text from the affected performance-step names.

Temporary branch triggers, scratch-registry publishing, runtime probes, and chained validation jobs have been removed. Validation results remain recorded in the PR comments.

Validation

  • Built both ROCm 10 images and exercised the complete AMD PR/nightly suites with the default AITER pin: run 33052814298.
  • Repeated both builds and suites with AITER a6d2b564fd671724a3720b8edf70e8d674e4d694: run 33055565205.
  • Verified that each image contains only its target architecture's device wheels.
  • Passed the current PR lint and local workflow, Dockerfile, shell-syntax, and whitespace checks.

References


CI States

Latest PR Test (Base): ✅ Run #33161266798
Latest PR Test (Extra): ❌ Run #33161266722
Latest PR Test (AMD ROCm 7.2): ❌ Run #33161266823

Build gfx942 and gfx950 images from AMD's prerelease wheel stack and wire targeted MI300/MI35x performance validation through the scratch registry.
@github-actions github-actions Bot added the amd label Aug 26, 2026
@bingxche

bingxche commented Aug 26, 2026 •

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Validation scope has been expanded to the complete existing AMD PR and nightly suites in run 32932367013.

After both gfx942 and gfx950 images are published, the release workflow now invokes:

  • pr-test-amd-rocm720.yml with rocm_version=rocm10rc4, run_all_tests=true, and runner_arch=mi300. This covers the generic MI300 lanes, the workflow's fixed MI35x lanes, the AMD extra suite, and disaggregation.
  • nightly-test-amd-rocm720.yml with rocm_version=rocm10rc4 and job_filter=all. This runs the complete MI300 + MI35x nightly job graph with RC4 as the single image flavor.

The PR, extra, nightly, normal-container, and disaggregated-container paths all route rocm10rc4 to bingxche/sgl-test; released ROCm flavors continue to use rocm/sgl-dev.

Experiment record

Both baseline images using AITER c16d44b93a528b2a4bfd6d8d3409116d465872a9 published successfully:

The same workflow has now started both complete validation graphs with rocm_version=rocm10rc4:

@bingxche

bingxche commented Aug 26, 2026 •

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ROCm 10 RC4 + AITER a6d2b564 comparison lane

A second, isolated image/test lane is running with AITER a6d2b564fd671724a3720b8edf70e8d674e4d694:

  • Build and validation run: #32937606479
  • Test branch: codex/rocm10-rc4-aiter-a6d2b564
  • Published image tags: rocm10rc4-aiter-a6d2b564-mi30x and rocm10rc4-aiter-a6d2b564-mi35x
  • Validation coverage: full AMD PR suite (run_all_tests=true) and full AMD nightly suite (job_filter=all)

The workflow verifies both the image's AITER_COMMIT stamp and /sgl-workspace/aiter git HEAD before pushing. This lane uses separate tags, branch, workflow, and concurrency from the c16d44 baseline, so it will not overwrite or cancel the baseline run.

Experiment record

Both comparison images pinned to AITER a6d2b564fd671724a3720b8edf70e8d674e4d694 published successfully:

The same workflow has started both complete validation graphs with rocm_version=rocm10rc4-aiter-a6d2b564:

@bingxche bingxche changed the title [AMD] Add ROCm 10.0 RC4 (gfx942 / gfx950) validation [AMD] Add ROCm 10.0.0 GA (gfx942 / gfx950) validation Aug 27, 2026
@bingxche

bingxche commented Aug 27, 2026 •

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ROCm 10.0.0 GA + AITER c16d44b baseline lane

This is the GA continuation of the RC4 baseline, pinned to AITER c16d44b93a528b2a4bfd6d8d3409116d465872a9:

Experiment record

After both images published, the same workflow automatically dispatched both complete validation graphs with rocm_version=rocm1000:

Both suites are currently running or queued. This is the dedicated GA + baseline-AITER record; the two historical RC4 records remain separate.

@bingxche

bingxche commented Aug 27, 2026 •

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ROCm 10.0.0 GA + AITER a6d2b564 comparison lane

This is the GA comparison lane with AITER a6d2b564fd671724a3720b8edf70e8d674e4d694:

Experiment record

After both images published, the same workflow automatically dispatched both complete validation graphs with rocm_version=rocm1000-aiter-a6d2b564:

Both suites are currently running or queued. The workflow verified the image's AITER commit stamp and /sgl-workspace/aiter git HEAD before publication. This record remains independent of the historical RC4 + a6d2b564 record.

yctseng0211 added a commit that referenced this pull request Aug 27, 2026
The upstream GA switch (#36434) reserves gfx1250 in ROCM_DEVICE_ARCH_LIST but
stops short of the CI-side detection, which still matched only gfx942/gfx950.
A gfx1250-rocm1000 image therefore fell through to the inference branch, where
its PIP_CONSTRAINT stamp made it look like a rocm724 gfx942 image and skewed
both the AITER pin lookup and MORI_GPU_ARCHS.
@bingxche bingxche changed the title [AMD] Add ROCm 10.0.0 GA (gfx942 / gfx950) validation [AMD] Add ROCm 10 (gfx942 / gfx950) release images Aug 28, 2026
@bingxche
bingxche marked this pull request as ready for review August 28, 2026 09:11
yctseng0211 added a commit that referenced this pull request Aug 28, 2026
Four shared build steps on this branch differ from the ROCm 10 release images,
so a gfx942 or gfx950 build here does not produce what #36434 validated. None of
them exist for the CDNA archs' sake, so put those archs back on the released
path and leave gfx1250 on exactly what it was brought up against.

The srt_hip_torch2_11 extras were renamed from srt_hip_rocm724 when the ROCm
7.14 flavor arrived, so that one extra could name a torch generation rather than
a ROCm flavor and serve 7.2.4, 7.14 and 10.0.0 alike. With 7.14 gone the
consumers are 7.2.4 and 10.0.0 again, which is what the upstream name already
covers. The lists are identical line for line, so this is a rename back. It also
repairs the AMD installer, which asks for dev_hip_rocm724.

The MORI RDMA/MPI/gRPC packages and the wider libabsl removal both arrived with
the gfx1250 bring-up. gfx1250 keeps them; the CDNA images go back to the package
set and the -dev-only removal they were released with. Dropping libabsl20220623
takes out the runtime library that components built earlier in the file link
against, which is what the comment directly above it warns not to do.

The rocm720 torch METADATA patch was generalized to also serve 7.14. That other
consumer is gone, and the rewrite turned a missing triton pin from a hard
failure into a silent skip, so restore the released version.

Left alone deliberately: PYTORCH_ROCM_ARCH and the pip constraints file. The
first is load-bearing for gfx1250 (tilelang reads the global value and has no
per-build override), and the second is what keeps pip from moving torch out from
under the gfx1250 image during the extras install.

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@HaiShaw HaiShaw left a comment

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LGTM

@HaiShaw
HaiShaw merged commit 9579bff into main Aug 28, 2026
118 of 124 checks passed
@HaiShaw
HaiShaw deleted the codex/rocm10-rc4-gfx942-950 branch August 28, 2026 15:03
@yctseng0211 yctseng0211 mentioned this pull request Aug 30, 2026
5 tasks
XinyuJiangCMU added a commit to XinyuJiangCMU/miles that referenced this pull request Sep 1, 2026
The wheel-SDK base ships the devel tree's runtime libs as byte-identical
copies of the core/libraries ones (ROCm/TheRock#7818), and devel/lib puts
unversioned *.so aliases on LD_LIBRARY_PATH, so an unversioned dlopen
(torch: libamd_smi.so; triton/proton: libamdhip64.so, libhsa-runtime64.so,
libhipblaslt.so) pulls a second copy of an already-loaded runtime into the
process. Two comgr copies abort at startup with LLVM's "Option registered
more than once"; the base image already collapses the libamd_smi pair,
where the second copy silently breaks device enumeration
(sgl-project/sglang#36434). Collapse every byte-identical top-level devel
duplicate back onto its original.
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3 participants